DG401 Datasheet, PDF (7/10 Pages) Intersil Corporation – Monolithic CMOS Analog Switches

DG401/403/405
Schematic Diagram (Typical Channel)
V+
V_L
V_IN
GND
V–
Test Circuits
Level
Shift/
Drive
Figure 1.
S
V–
V+
D
V_O is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of
the output waveform.
+5 V
+15 V
3V
Logic
50%
Input
0V
t_r <20 ns
t_f <20 ns
V_L
V+
"10 V
S
D
Switch
Input*
V_S
V_O
90%
t_OFF
V_O
IN
R_L
C_L
GND
V–
1 kW
35 pF
Switch ^{0 V}
Output
t_ON
–15 V
90%
Switch
Input*
–V_S
V_O
C_L (includes fixture and stray capacitance)
V_O = V_S
R_L
R_L + r_DS(on)
*V_S = 10 V for t_ON, V_S = –10 V for t_OFF
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
Figure 2. Switching Time
+5 V
V_L
V_S1
S₁
V_S2
S₂
IN
GND
+15 V
V+
D₁
D₂
V–
–15 V
Logic
3V
Input
0V
V_O1
V_S1
V_O1
V_O2
R_{L1 CL1}
Switch _{0 V}
Output _VS2
V_O2
R_{L2 CL2}
Switch ^{0 V}
Output
C_L (includes fixture and stray capacitance)
Figure 3. Break-Before-Make
50%
90%
90%
t_D
t_D
Siliconix
7
S-53748—Rev. E, 05-Jun-97