U3550BM Datasheet, PDF (5/25 Pages) TEMIC Semiconductors – Low-Power FM Transmitter / Synthesizer System 26 to 50 MHz

U3550BM
Modulator PLL
The fractional divider has been chosen to increase
+ ń ǒ ) Ǔ reference the frequency of the modulator PLL.
Q
557.5 kHz f_mod P ₂₂₃
P: integer part of the fractional divider
+ ǒ Ǔ ^{Q: fractional part of the fractional divider}
Q 223
f_mod
557.5 kHz
–P
+ 223
557.7 kHz
2.5 kHz
The frequency step 2.5 kHz is a fraction of the reference
frequency 557.5 kHz
³ ) ) + ) Qx (P 1) (223–Q)P
223
P
Q
223
For each comparison cycle (f_Ref1 = 557.5 kHz), the accu-
mulator content is incremented by the Q value and the
divider divides by the P value. When the accumulator
value reaches or exceeds 223, the divider divides by the
value (P + 1). Then, the accumulator holds the excess
value (accumulator value – 223). After 223 cycles, the
correct division is executed.
Local Oscillator PLL
+ f_Ref3
f_LO
N
Serial Bus Interface
The circuit is remoted by an external microcontroller
through the serial bus.
The data is a 12-bit word:
A0 – A3: address of the destination register (0 to 15)
D0 – D7: contents of register
The data line must be stable when the clock is high and
data must be shifted serially.
After a 12-clock period, the transfer to the destination
register is generated (internally) by a low-to-high
transition of the data line when the clock is high.
Micro-
processor
Data
Clock
Figure 4.
D
C
96 11787
Data
(D)
Clock
(C)
13279
D0 D1 D2
A0 A1 A2 A3
1st word
Word transmission
Figure 5. Serial bus transmission
2nd word
Transfer condition
Rev. A2, 10-Sep-98
5 (25)
Preliminary Information