U4091BM Datasheet, PDF (16/29 Pages) TEMIC Semiconductors – Programmable Telephone Audio Processor

U4091BM
Analog-to-Digital Converter ADC
This circuit is a 7-bit successive approximation analog-
to-digital converter in switched capacitor technique. An ^SOC
internal bandgap circuit generates a 1.25-V reference
voltage which is the equivalent of 1 MSB.
1LSB = 19.5 mV. The possible input voltage at ADIN is _EOC
0 to 2.48 V.
50 µs
14594
The ADC needs an SOC (Start Of Conversion) signal. In
Figure 16. Timing of ADC
the ‘High’ phase of the SOC signal, the ADC is reset.
50 ms after the beginning of the ‘Low’ phase of the SOC
signal, the ADC generates an EOC (End Of Conversion)
signal which indicates that the conversion is finished. The ^{IL 20mV/(1mA S)}
SOC
rising edge of EOC generates an interrupt at the INT
ADIN
output. The result can be read out by the serial bus.
0.4 VB
MSB
Voltages higher than 2.45 V have to be divided. The
signal which is connected to the ADC is determined by
5 bits: ADC0, ADC1, ADC2, ADC3 and NWT.
TLDR/TLDT measuring is possible relative to a preced-
0.4 VMPS
0.75 VMP
8 (TLDR–REF)
ADC
BIT5
BIT4
BIT3
ing reference measurement. The current range of IL can
8 (TLDT–REF)
BIT2
be doubled by ADCR. If ADCR is ‘High’, S has the value
0.4 SAO1
BIT1
0.5, otherwise S = 1.
0.4 OFF1
LSB
W ^{The source impedance at ADIN must be lower than}
250 k .
Accuracy: 1 LSB + 3%
0.4 OFF2
0.4 OFF3
EOC
14595
Figure 17. ADC input selection
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D = measured digital word (0 < = D < = 127)
S = programmable gain 0.5 or 1
Vp = peak value of the measured signal
16 (29)
Target Specification
Rev. A1, 02-Jun-98