TSC691E Datasheet, PDF (13/142 Pages) TEMIC Semiconductors – RT Integer Unit for Embedded Real time 32-bit Computer

TSC691E
2. TSC691E OVERVIEW
2.1. SPARC RISC STANDARD FUNCTIONS :
D Full binary compatibility with entire SPARC V7.0 application software base
D Architecture efficiency that sustains 1.25 to 1.5 clocks per instruction
D Large windowed register file
D Tightly coupled floating-point interface
D User/supervisor modes for multitasking
D Semaphore instructions and alternate address spaces for multiprocessing
2.2. Fault Tolerant and Test Mechanism Improvements:
D Parity checking on 98.7% of the total number of latches with hardware error traps
D Parity checking of address, data pads and control pads
D Program flow control
D Master/Checker operation
D IEEE Standard Test Access Port & Boundary-Scan Architecture
D Possibility to disable the bus parity checking
D Manufactured using TEMIC Space hardened 0.8 µm SCMOS RT TECHNOLOGY
D Part of the ERC32 high performance 32-bit computing core
To support applications requiring an extremely high level of reliability, the following improvements were introduced
in the standard SPARC RISC processor TSC691:
D Several independent fault detection MECHANISMs to support the design of fault tolerant systems
D Such as odd parity checking, Program Flow Control and Master/Checker operations.
D Support of sophisticated PC board level test using the IEEE Standard Test Access Port and
D Boundary Scan Architecture
D Hardening of the process by construction, applying restricted full static CMOS design rules for
D all critical blocks of the circuit such as register file, PLAs, ROMs etc...
D Hardened device processing using the TEMIC 0.8 µm SCMOS-RT TECHNOLOGY.
Thanks to careful handling of the improvements, the introduced modifications have neither reduced
the performance of the device nor changed the full binary compatibility with the entire SPARC V7.0
application software.
2.3. Presentation of the ERC32 computing core
The TSC691E Integer Unit is, with the TSC692E Floating Point Unit and the TSC693E (Memory controller), a part
of the ERC32 computing core.
2.3.1. Concept
The objective of the ERC32 is to provide a high performance 32-bit computing core, with which computers for
on-board embedded real-time applications can be built. The core will be characterized by low circuit complexity and
power consumption. Extensive concurrent error detection and support for fault tolerance and reconsideration will also
be emphasized.
In addition to the main objective the ERC32 core should be possible to use for performance demanding research
applications in deep space probes. The radiation tolerance and error masking are therefore important. For the real-time
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MATRA MHS
Rev. H (02 Dec. 96)