TSC691E Datasheet, PDF (108/142 Pages) TEMIC Semiconductors – RT Integer Unit for Embedded Real time 32-bit Computer

TSC691E
3.8.2.10. Window overflow
This trap occurs when the continued execution of a SAVE instruction would cause the CWP to point to a window
marked invalid in the WIM register.
3.8.2.11. Window underflow
This trap occurs when the continued execution of a RESTORE instruction would cause the CWP to point to a window
marked invalid in the WIM register. The window underflow trap type can also be set in the PSR during a RETT
instruction, but the trap taken is a reset. See Section 3.8.1 on reset traps and SPARC V7.0 Instruction Set for the
instruction definition for RETT.
3.8.2.12. Memory address not aligned
Memory address not aligned trap occurs when a load or store instruction generates a memory address that is not properly
aligned for the data type or if a JMPL instruction generates a PC value that is not word aligned (low-order two bits
nonzero).
3.8.2.13. Tag overflow
This trap occurs if execution of a TADDccTV or TSUBccTV instruction causes the overflow bit of the integer condition
codes to be set. See the instruction definitions of TADDccTV and TSUBccTV and Section 3.4.3.2.3 for details.
3.8.2.14. Trap instruction
This trap occurs when a Ticc instruction is executed and the trap conditions are met. There are 128 programmable trap
types available within the trap instruction trap (see SPARC V7.0 Instruction Set, Ticc instruction).
MATRA MHS
97
Rev. H (02 Dec.96)