TSC691E Datasheet, PDF (103/142 Pages) TEMIC Semiconductors – RT Integer Unit for Embedded Real time 32-bit Computer

TSC691E
CLK
FEXC
FXACK
FLUSH
Figure 57. Floating–Point Exception Handshake Timing
1
2
3
4
5
6
CLK
A<31:0> ^A1
A2
A3
A4
T0
T1
D<31:0> ^{Inst 0}
Inst 1
Inst 2
Inst 3
Inst 4
Trap 0
IRL<3:0>
0H
INTACK
Interrupt Asserted
Don’t care until RETT
Figure 58. Asynchronous Interrupt Timing
3.7.14. Floating-Point Exceptions
The floating–point unit asserts FEXC to notify the TSC691E that a floating-point exception has occurred and that it
should take a trap on the next floating-point instruction that it encounters in the instruction stream (see Figure 57 ).
The TSC691E asserts FXACK to signal the FPU that the trap is being taken, and FLUSH to clean out the FPU’s decode
buffers. From this point on, the FPU will execute only floating-point store queue instructions until its queue is emptied
by the trap handler.
FEXC is deasserted by the FPU after FXACK is asserted. FXACK is deasserted by the TSC691E after FEXC is
deasserted.
3.7.15. Interrupts
The asynchronous IRL<3:0> inputs are sampled on the rising edge of every clock. If the interrupt value represented
by those inputs is greater than the masking value in the processor, and no higher priority trap supersedes it, the
TSC691E will take the interrupt. The IRL input level should be held stable until the processor asserts INTACK.When
the trap is taken, IRL line are ignored until ET=0 (until RETT instruction is executed). Figure 58 shows the timing
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MATRA MHS
Rev. H (02 Dec.96)