TMS29LF800T Datasheet, PDF (27/49 Pages) Texas Instruments – Array-Blocking Architecture

erase and program performance^†
TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Sector-erase time
Program time
Chip-programming time
Excludes 00H programming prior to
erasure
Excludes system-level overhead
Excludes system-level overhead
1‡
15§
s
9
9 3 600§ µs
6‡
50§
s
Erase/program cycles
100 000 1 000 000
cycles
† _{The internal algorithms allow for 2.5-ms/byte program time. DQ5 = 1 only after a byte takes the theoretical maximum time to program. A minimal}
number of bytes can require signficantly more programming pulses than the typical byte. The majority of the bytes program within one or two
pulses. This is demonstrated by the typical and maximum programming time listed above.
‡ _{25°C, 3-V VCC, 100 000 cycles, typical pattern}
§ _{Under worst-case conditions: 90°C, 2.7-V VCC, 100 000 cycles}
latchup characteristics (see Note 10)
PARAMETER
Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE)
Input voltage with respect to VSS on all I/O pins
Current
NOTE 10: Includes all pins except VCC test conditions: VCC = 3 V, one pin at a time
MIN
–1
–1
– 100
MAX
13
VCC + 1
100
UNIT
V
V
mA
pin capacitance, all packages (see Note 11)
PARAMETER
CIN
Input capacitance
COUT Output capacitance
CIN2 Control pin capacitance
NOTE 11: Test conditions: TA = 25°C, f = 1 MHz
TEST CONDITIONS
VIN = 0
VOUT = 0
VIN _{= 0}
TYP MAX UNIT
6 7.5 pF
8.5
12 pF
8
10 pF
data retention
PARAMETER
Minimum pattern data retention time
TEST CONDITIONS
150°C
125°C
MIN MAX UNIT
10
Years
20
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