TMS29LF800T Datasheet, PDF (18/49 Pages) Texas Instruments – Array-Blocking Architecture

TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997
hardware-reset bit (RESET) (continued)
Asserting RESET during program or erase can leave erroneous data in the address locations. These locations
need to be updated after the device resumes normal operations. A minimum of 50 ns must be allowed after
RESET goes high before a valid read can take place.
tRL = 500 ns
RESET
RY/BY
20 µs max
Figure 1. Device Reset During a Program or Erase Operation
RESET
tRL = 500 ns
RY/BY
0V
Figure 2. Device Reset During Read Mode
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