TMS29LF800T Datasheet, PDF (1/49 Pages) Texas Instruments – Array-Blocking Architecture

D Single Power Supply Supports 2.7-V and
3.6-V Read/Write Operation
D Organization
1 048 576 By 8 Bits
524 288 By 16 Bits
D Array-Blocking Architecture
– One 16K-Byte/One 8K-Word Boot Sector
– Two 8K-Byte/4K-Word Parameter Sectors
– One 32K-Byte/16K-Word Sector
– Fifteen 64K-Byte/32K-Word Sectors
– Any Combination of Sectors Can Be
Erased. Supports Full-Chip Erase
– Any Combination of Sectors Can Be
Marked as Read-Only
D Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector
D Sector Protection
– Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
D Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases
Any Sector
– Automatically Programs and Verifies the
Program Data at Specified Address
D JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM
Command Set
D Fully Automated On-Chip Erase and
Program Operations
D 100 000 Program/Erase Cycles
D Low Power Dissipation
– 20-mA Typical Active Read for Byte Mode
– 28-mA Typical Active Read for Word
Mode
– 30-mA Typical Program/Erase Current
– Less Than 60-µA Standby Current
– 5 µA in Deep Power-Down Mode
D All Inputs/Outputs TTL-Compatible
TMS29LF800T, TMS29LF800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS828B – SEPTEMBER 1996 – REVISED OCTOBER 1997
D Erase Suspend/Resume
– Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
D Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
D Package Options
– 44-Pin Plastic Small-Outline Package
(PSOP) (DBJ Suffix)
– 48-Pin Thin Small-Outline Package
(TSOP) (DCD Suffix)
D Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
– Hardware Method for Detection of
Program/Erase Cycle Completion
Through Ready/Busy (RY/BY) Output Pin
" D High-Speed Data Access at 3.3-V
V_CC 10% at Three Temperature Ranges
– 90 ns Commercial . . . 0°C to 70°C
– 100 ns Extended . . . –40°C to 85°C
– 120 ns Automotive . . . –40°C to 125°C
A[0:18]
BYTE
DQ[0 :14]
DQ15/A–1
CE
OE
NC
RESET
RY / BY
VCC
VSS
WE
PIN NOMENCLATURE
Address Inputs
Byte/Word Enable
Data In / Data out
Data In/Out (Word-Wide mode)
Low-Order Address (Byte-Wide mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
Ready / Busy Output
Power Supply
Ground
Write Enable
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1997, Texas Instruments Incorporated
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