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PCM1860 Datasheet, PDF (32/115 Pages) Texas Instruments – 4ch Audio ADCs With Universal Front End
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PCM1860, PCM1862, PCM1864, PCM1864-Q1
SLASE55A – NOVEMBER 2014 – REVISED DECEMBER 2014
www.ti.com
fS
8 kHz
16 kHz
48 kHz
96 kHz
192 kHz
SCK Ratio
128
256
384
512
768
128
256
384
512
768
128
256
384
512
768
128
256
384
512
128
256
SCK
Frequency
(MHz)
1.024
2.048
3.072
4.096
6.144
2.048
4.096
6.144
8.192
12.288
6.144
12.288
18.432
24.576
36.864
12.288
24.576
36.864
49.152
24.576
49.152
Table 9. PCM1862 Clock Divider and Source Control In The Presence Of External SCK
PLL Ratio
12288
12288
12288
6144
6144
6144
2048
2048
2048
1024
1024
1024
512
512
PLL
Frequency
(MHz)
98.304
98.304
98.304
off
off
98.304
98.304
98.304
off
off
98.304
98.304
98.304
off
off
98.304
98.304
98.304
off
98.304
98.304
PLL
DSP1 Clock
Configuration (MHz)
P=0,R=1,
J=48, D=0
2.048
P=0,R=1,
J=24, D=0
2.048
P=0,R=1,
J=16, D=0
2.048
2.048
3.072
P=0,R=1,
J=24, D=0
4.096
P=0,R=1,
J=12, D=0
4.096
P=0,R=1, J=8, 6.144
D=0
4.096
6.144
P=0,R=1, J=8, 12.288
D=0
P=1,R=1, J=8, 12.288
D=0
P=2,R=1, J=8, 18.432
D=0
12.288
18.432
P=3,R=1,
J=16, D=0
24.756
P=7,R=1,
J=16, D=0
24.756
P=11,R=1,
J=16, D=0
24.756
24.756
P=3,R=1, J=8, 49.152
D=0
P=7,R=1, J=8, 49.152
D=0
DSP1 Clock
Source
PLL
SCK
SCK
SCK
SCK
PLL
SCK
SCK
SCK
SCK
PLL
SCK
SCK
SCK
SCK
PLL
SCK
SCK
SCK
PLL
SCK
Divider
48
1
1
2
2
24
1
1
2
2
8
1
1
2
2
4
1
1
2
2
1
DSP 2 Clock DSP2 Clock
(MHz)
Source
2.048
PLL
Divider
48
2.048
SCK
1
2.048
SCK
1
2.048
SCK
2
3.072
SCK
2
4.096
PLL
24
4.096
SCK
1
6.144
SCK
1
4.096
SCK
2
6.144
SCK
2
12.288
PLL
8
12.288
SCK
1
18.432
SCK
1
12.288
SCK
2
18.432
SCK
2
24.756
PLL
4
24.756
SCK
1
24.756
SCK
1
24.756
SCK
2
49.152
PLL
2
49.152
SCK
1
ADC Clock
(MHz)
1.024
1.024
1.024
1.024
1.024
2.048
2.048
2.048
2.048
2.048
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
6.144
ADC Clock
Source
PLL
SCK
SCK
SCK
SCK
PLL
SCK
SCK
SCK
SCK
PLL
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
Divider
96
2
3
4
6
48
2
3
4
6
16
2
3
4
6
2
4
6
8
4
8
32
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