TL071_16 Datasheet, PDF (17/51 Pages) Texas Instruments – Low-Noise JFET-Input Operational Amplifiers

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TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
SLOS080M – SEPTEMBER 1978 – REVISED JUNE 2015
System Examples (continued)
88.4 kΩ
18 pF
6 sin ωt
18 pF
VCC+
TL072
88.4 kΩ
VCC−
1N4148
18 pF
VCC+
TL072
VCC−
1N4148
18 kΩ (see Note A)
−15 V
1 kΩ
1 kΩ
15 V
18 kΩ (see Note A)
88.4 kΩ
6 cos ωt
0.1 µF
10 kΩ
10 kΩ
IN−
50 Ω
IN+
0.1 µF
10 kΩ
V_CC+
TL071
N2
N1
1 MΩ
OUT
100 kΩ
Figure 27. 100-kHz Quadrature Oscillator
10 Power Supply Recommendations
Figure 28. AC Amplifier
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a
dual-supply can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
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