NUC120VE3AN Datasheet, PDF (370/600 Pages) Nuvotem Talema – NuMicro™ Family NUC100 Series Technical Reference Manual

NuMicro™ NUC100 Series Technical Reference Manual
5.10.6 Register Description
Timer Control Register (TCSR)
Register
Offset
R/W Description
TCSR0
TMR_BA01+0x00 R/W Timer0 Control and Status Register
TCSR1
TMR_BA01+0x20 R/W Timer1 Control and Status Register
TCSR2
TMR_BA23+0x00 R/W Timer2 Control and Status Register
TCSR3
TMR_BA23+0x20 R/W Timer3 Control and Status Register
Reset Value
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
31
Reserved
23
30
CEN
22
15
14
7
6
29
28
27
IE
MODE[1:0]
21
20
19
Reserved
13
12
11
Reserved
5
4
3
PRESCALE[7:0]
26
CRST
18
10
2
25
CACT
17
9
24
CTB
16
TDR_EN
8
1
0
Bits
[31]
[30]
[29]
[28:27]
Descriptions
Reserved
CEN
IE
MODE
Reserved
Timer Enable Bit
1 = Starts counting
0 = Stops/Suspends counting
Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up
counting from the last stop counting value.
Note2: This bit is auto-cleared by hardware in one-shot mode (MODE [28:27] =00)
when the associated timer interrupt is generated (IE [29] =1).
Interrupt Enable Bit
1 = Enable timer Interrupt
0 = Disable timer Interrupt
If timer interrupt is enabled, the timer asserts its interrupt signal when the associated
up-timer value is equal to TCMPR.
Timer Operating Mode
MODE
Timer Operating Mode
00
The timer is operating in the one-shot mode. The associated interrupt
signal is generated once (if IE is enabled) and CEN is automatically
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Publication Release Date: Dec. 22, 2010
Revision V1.06