NUC120VE3AN Datasheet, PDF (219/600 Pages) Nuvotem Talema – NuMicro™ Family NUC100 Series Technical Reference Manual

NuMicro™ NUC100 Series Technical Reference Manual
mode. Furthermore, a user can write 0 into USB_ATTR[4] to turn off PHY under special
circumstances like suspend to save power.
5.4.4.7 Buffer Control
There is 512 bytes SRAM in the controller and the 6 endpoints share this buffer. The user shall
configure each endpoint’s effective starting address in the buffer segmentation register before the
USB function active. The BUFFER CONTROL block is used to control each endpoint’s effective
starting address and its SRAM size is defined in the MXPLD register.
Figure 5-11 depicts the starting address for each endpoint according the content of BUFSEG and
MXPLD registers. If the BUFSEG0 is programmed as 0x08h and MXPLD0 is set as 0x40h, the
SRAM size of endpoint 0 is start from USB_BA + 0x108h and end in USB_BA + 0x148h. (Note:
the USB SRAM base is USB_BA + 0x100h).
BUFSEG0 = 0x008
BUFSEG1 = 0x048
BUFSEG2 = 0x088
USB SRAM Start Address
Setup Token Buffer: 8 bytes
EP0 SRAM Buffer: 64 bytes
EP1 SRAM Buffer: 64 bytes
EP2 SRAM Buffer
USB SRAM = USB_BA + 0x0100h
EP0 SA = USB_BA + 0x0108h
MXPLD0 = 0x40
EP1 SA = USB_BA + 0x0148h
MXPLD1 = 0x40
EP2 SA = USB_BA + 0x0188h
512
Bytes
BUFSEG3 = 0x100
EP3 SRAM Buffer
EP3 SA = USB_BA + 0x0200h
Figure 5-11 Endpoint SRAM Structure
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Publication Release Date: Oct 22, 2010
Revision V1.06