M054LAN Datasheet, PDF (29/64 Pages) Nuvotem Talema – ARM Cortex™-M0 32-BIT MICROCONTROLLER

64M052/M054 Data Sheet
PCLK
W D T _ E N (A P B C L K 1 [0 ])
W a tc h D o g T im e r
T M R 0 _ E N (A P B C L K 1 [2 ])
T M R 1 _ E N (A P B C L K 1 [3 ])
T im e r0
T im e r1
T M R 2 _ E N (A P B C L K 1 [4 ])
T im e r2
T M R 3 _ E N (A P B C L K 1 [5 ])
T im e r3
F D IV _ E N (A P B C L K 1 [6 ])
F re q u e n c y D iv id e r
I2 C 0 _ E N (A P B C L K 1 [8 ])
S P I0 _ E N (A P B C L K 1 [1 2 ])
S P I1 _ E N (A P B C L K 1 [1 3 ])
U A R T 0 _ E N (A P B C L K 1 [1 6])
U A R T 1 _ E N (A P B C L K 1 [1 7 ])
P W M 0 1 _ E N (A P B C L K 1 [2 0 ])
P W M 2 3 _ E N (A P B C L K 1 [2 1 ])
P W M 4 5 _ E N (A P B C L K 1 [2 2 ])
P W M 6 7 _ E N (A P B C L K 1 [2 3 ])
I2 C
S P I0
S P I1
U A R T0
U A R T1
PW M 01
PW M 23
PW M 45
PW M 67
Figure 6–7 Peripherals Clock Source Select for PCLK
6.3.6 Power Down Mode (Deep Sleep Mode) Clock
When chip enter into power down mode, most of clock sources, peripheral clocks and system
clock will be disabled. Some of clock sources and peripherals clock are still active in power down
mode.
For theses clocks which still keep active list below:
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Publication Release Date: Mar 15, 2011
Revision V1.0