SM89516A Datasheet, PDF (9/25 Pages) SyncMOS Technologies,Inc – 8 - Bit Micro-controller with 64KB flash 1KB RAM embedded

SyncMOS Technologies Inc.
September 2002
SM89516A
Data Bank Control Register (DBANK, $86)
bit-7
bit-0
BSE
Unused Unused Unused
BS3
BS2
BS1
BS0
Read / Write: R/W
-
-
-
R/W
R/W
R/W
R/W
Reset value:
0
*
*
*
0
0
0
1
Data bank select enable bit BSE = 1 enables the data bank select function
Data bank select enable bit BSE = 0 disables the data bank select function
BS[3:0] setting will map $040~$07F RAM space to entire 1K byte on-chip RAM space.
Internal RAM Control Register (RCON, $85)
Read / Write:
Reset value:
bit-7
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
RAMS1
R/W
0
bit-0
RAMS0
R/W
0
SM89516A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By
instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1,
RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0).
RAMS1
0
0
1
RAMS0
0
1
0
MOVX @Ri i=0,1 mapping to expended RAM address
$0000 ~ $00FF
$0100 ~ $01FF
$0200 ~ $02FF
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
Read / Write:
Reset value:
bit-7
WDR
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
OME
R/W
0
bit-0
ALEI
R/W
0
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow. WDR will be set to 1, The bit 7 (WDR)
of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User
should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/25
Ver 1.2 SM89516A 09/02