SM89516A Datasheet, PDF (13/25 Pages) SyncMOS Technologies,Inc – 8 - Bit Micro-controller with 64KB flash 1KB RAM embedded

SyncMOS Technologies Inc.
September 2002
SM89516A
5.2 SPWM Registers - P1CON, SPWMC, SPWMD[4:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
bit-0
SPWME4 SPWME3 SPWME2 SPWME1 SPWME0 Unused Unused Unused
Read / Write:
R/W
R/W
R/W
R/W
R/W
-
-
-
Reset value:
0
0
0
0
0
*
*
*
SPWME[4:0] : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset
to zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, $A3)
Read / Write:
Reset value:
bit-7
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
SPFS1
R/W
0
SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
bit-0
SPFS0
R/W
0
SPFS1
0
0
1
1
SPFS0
0
1
0
1
Divider
2
4
8
16
SPWM clock, Fosc=20MHz
10MHz
5MHz
2.5MHz
1.25MHz
SPWM clock, Fosc=24MHz
12MHz
6MHz
3MHz
1.5MHz
SPWM Registers - SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4)
Read / Write:
Reset value:
bit-7
SPWMD
[4:0]4
R/W
0
SPWMD
[4:0]3
R/W
0
SPWMD
[4:0]2
R/W
0
SPWMD
[4:0]1
R/W
0
SPWMD
[4:0]0
R/W
0
BRM
[2:0]2
R/W
0
BRM
[2:0]1
R/W
0
bit-0
BRM
[2:0]0
R/W
0
SPWMD[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/25
Ver 1.2 SM 89516A 09/02