SM5952E Datasheet, PDF (50/53 Pages) SyncMOS Technologies,Inc – 256 bytes SRAM as standard 8052

SM5952E
8-Bit Micro-controller
8KB with 4KB ISP Flash
& 1KB RAM embedded
14.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be
protected (locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash
memory program/erase timing so the locked ISP service program can not be erased by flash erase function. If user
needs to erase the locked ISP service program, he can do it by writer only. User can not change ISP service
program when SM5952E was in system.
14.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program
and execute it. There are three ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start
address of ISP service program.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) RESET is asserted with P2.6 and P2.7 both at low state. The default is enable. User can change
enable or disable by writer.
(4) RESET is asserted with P4.3. The default is enable. User can change enable or disable by writer.
During the strobe window, the hardware will detect the status of P2.6&P2.7 or P4.3. If they meet one of above
conditions, chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the
SM5952E, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
P2.6
P2.7
RST
100ms
100ms
P4.3
RST
100ms
100ms
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M091
Ver C SM5952E 04/17/2015
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