SM5952E Datasheet, PDF (43/53 Pages) SyncMOS Technologies,Inc – 256 bytes SRAM as standard 8052

SM5952E
8-Bit Micro-controller
8KB with 4KB ISP Flash
& 1KB RAM embedded
The wake-up is initiated by an interrupt event at INT 0 or INT 1 pin, and is followed by an internal clock de-bouncing
procedure. The de-bouncing logic effectively avoids CPU to run at unstable clock oscillation.
Mode
Idle
Idle
Power-Down
Power-Down
Pin Status in IDLE Mode and Power-Down Mode
Program Memory
ALE
PSEN
Port0
Port1
Internal
1
1
Data
Data
External
1
1
Float
Data
Internal
0
0
Data
Data
External
0
0
Float
Data
Port2
Data
Address
Data
Data
Port3
Data
Data
Data
Data
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M091
Ver C SM5952E 04/17/2015
- 43 -