SM5952E Datasheet, PDF (12/53 Pages) SyncMOS Technologies,Inc – 256 bytes SRAM as standard 8052

Function Description
SM5952E
8-Bit Micro-controller
8KB with 4KB ISP Flash
& 1KB RAM embedded
1. General Features
SM5952E is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the
following sections.
1.1 Embedded Flash
The program can be loaded into the embedded 8KB+4KB Flash memory via its writer or In-System Programming
(ISP).
1.2 IO Pads
The SM5952E has Five I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4. Port 0~Port 3 are 8-bit ports. Port 4 is 4-bit
port. These are: quasi-bidirectional (standard 8051 port outputs) with Port 1~4, and open drain with Port 0.
All the pads are with slew rate to reduce EMI. The IO pads can withstand ESD in human body mode guaranteeing
the SM5952E’s quality in high electro-static environments.
1.3 System Control Register (SCONF)
Mnemonic: SCONF
7
6
5
4
3
WDR
-
-
PDWUE
-
2
ISPE
1
OME
Address: BFh
0
Reset
ALEI
02H
WDR: Watch Dog Timer Reset.
When system reset by Watch Dog Timer overflow, WDR will be set to 1.
User should check WDR bit whenever un-predicted reset happened.
PDWUE: Power down wake-up enable bit.
Set 1 to enable wake-up from power-down state by external pin int0 or int1.
ISPE: ISP function enable bit.
When Enable the ISP function, ISPE will be set to 1.
OME: On-chip 768B expanded RAM enable bit.
Set 1 to enable on-chip 768B expanded RAM access.
ALEI: ALE output inhibit bit.
When default, It can inhibit the clock signal in (Fosc/6) Hz output to the ALE pin.
When set to 1, the ALE pin output will stop to reduce EMI.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M091
Ver C SM5952E 04/17/2015
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