SM5953 Datasheet, PDF (37/43 Pages) SyncMOS Technologies,Inc – Six interrupt sources with two priority levels

SM5953
8-Bit Micro-controller
15KB with ISP Flash
& 256B RAM embedded
Mnemonic Description Dir. Bit 7
WDTC
SCONF
Watchdog timer
control register
9FH
WDTE
System Control
Register
BFH
WDR
Mnemonic: WDTC
7
6
5
WDTE -
CLEAR
Bit 6 Bit 5
Watchdog Timer
-
CLEAR
Bit 4
-
-
-
-
Bit 3 Bit 2 Bit 1 Bit 0 RST
-
PS [2:0]
00H
-
ISPE
-
ALEI 00H
Address: 9Fh
4
3
2
1
0
Reset
-
-
PS [2:0]
00H
WDTE: Watch Dog Timer enable bit.
CLEAR: Watch Dog Timer clear bit.
If CLEAR bit set to1, setting this bit the Watchdog timer counter clear and re-start to
count from the Beginning.
PS[2:0]: Watch Dog timer over flow period setting.
Mnemonic: SCONF
7
6
5
WDR
-
-
Address: BFh
4
3
2
1
0
Reset
-
-
ISPE
-
ALEI 00H
WDR Watch Dog Timer Reset.
When system reset by Watch Dog Timer overflow, WDR will be set to 1.
User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M074
Ver D SM5953 04/16/2015
- 36 -