SM5953 Datasheet, PDF (18/43 Pages) SyncMOS Technologies,Inc – Six interrupt sources with two priority levels

SM5953
8-Bit Micro-controller
15KB with ISP Flash
& 256B RAM embedded
4. CPU Engine
The SM5953 engine is composed of four components:
(1) Control unit
(2) Arithmetic – logic unit
(3) Memory control unit
(4) RAM and SFR control unit
The SM5953 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following chapter describes the main engine register.
Mnemonic
Description
ACC
B
PSW
SP
DPL
DPH
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low
Data pointer high
Dir. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
8051 Core
E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
F0h B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
D0h CY
AC
F0
RS[1:0]
OV PSW.1 P
81h
SP[7:0]
82h
DPL[7:0]
83h
DPH[7:0]
RST
00H
00H
00H
07H
00H
00H
4.1 Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
5
ACC.7 ACC.6 ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0 00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2 B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
Address: F0h
7
6
5
4
3
2
1
0
Reset
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M074
Ver D SM5953 04/16/2015
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