SM89T16R1 Datasheet, PDF (19/34 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller With 64KB Flash ROM & IKB RAM & Two UART & RTC & ADC & PWM embedded

SyncMOS Technologies Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & Two UART & RTC & ADC & PWM embedded
JNZ
rel
Jump if A ≠ 0
2
3
JMP
@A+DPTR
Jump to A+ DPTR
1
2
DJNZ
Ri,rel
Decrement and jump if Rn not zero
2
3
DJNZ
Direct,rel
Decrement and jump if direct not zero
3
4
CJNE
A,direct,rel
Jump if A ≠ < direct >
3
4
CJNE
A,#data,rel
Jump if A ≠ < #data >
3
4
CJNE
@Ri,#data,rel
Jump if Rn ≠ < #data >
3
4
CJNE
Ri,#data,rel
Jump if @Ri ≠ < #data >
3
4
ACALL
Address11
Call Subroutine only at 2k bytes Address
2
3
AJMP
Address11
Jump only At 2k bytes addressing
2
3
LCALL
Address16
Call Subroutine in max 64K bytes Address
3
4
LJMP
Address16
Jump to max 64K bytes Address
3
4
SJMP
rel
Jump on at 256 bytes
2
3
RET
Return from subroutine
1
3
RETI
Return from interrupt
1
3
NOP
No Operation
1
1
Memory organization
Program memory
The program memory of SM89T16R1 consists of 64K bytes FLASH memory on chip. If during RESET, the /EA pin
was held HIGH, the SM89T16R1 does not execute out of the internal program memory. If the /EA pin was held LOW
during RESET the SM89T16R1 fetch all instructions from the external program memory.
Internal Data memory
The Data memory of SM89T16R1 consists of 1280 bytes internal data memory (256 bytes standard RAM and 1024
bytes AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX (Stretch=0, 2 machine
fixed)
Analog to Digital Converter (ADC)
The ADC Block Diagram Shown as below:
Those are only 4 pins mirror to Port 2[7:4] at Vin<3:0>. The Digital output DATA [7:0] were put into ADCD ($8FH).
And the ADC interrupt vector is 4BH.
The ADC SFR is shown as below:
ADSCR ($8EH)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
COM
CON
ADCSS1 ADCSS0
CH1
CH0
COM: Read only. When conversion complete, it will be set.
CON: when set, the ADC will conversion continuous, else it will conversion only once.
ADCSS [1:0]: ADC clock select. (ADC_CLK range 500 KHz~2.5 MHz).If over frequency of ADC_CLK, the
conversion data may be unstable.
CH [1:0]: ADC channel select.
ADCSS1
0
0
1
1
ADCSS0
0
1
0
1
ADC_CLK
FOSC/4
FOSC/8
FOSC/16
FOSC/32
CH1
CH0
Input select
0
0
CH0
0
1
CH1
1
0
CH2
1
1
CH3
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM89T16R1 V1.0 JANUARY 2005
19