SM89T16R1 Datasheet, PDF (11/34 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller With 64KB Flash ROM & IKB RAM & Two UART & RTC & ADC & PWM embedded

SyncMOS Technologies Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & Two UART & RTC & ADC & PWM embedded
t_AVDV2
9
t_QVWX
9
t_WHQX
9
t_RLAZ
8
t_WHLH
8,9
Port2 Address valid to /WR or /RD LOW
Data valid to /WR transition
Data hold after /WR
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
1.5t_CLCL–5
2.5 t_CLCL–5
-5
1.0 t_CLCL -5
1.0 t_CLCL -5
2.0 t_CLCL -5
0
1.0 t_CLCL -5
0.5 t_CLCL–5
10
1.0 t_CLCL +5
ns
t_MCS =0
t_MCS >0
ns
t_MCS =0
t_MCS >0
ns
t_MCS =0
t_MCS >0
ns
ns
t_MCS =0
t_MCS >0
Notes:
t_MCS is time period related to the Stretch memory cycle selection. The following table shows the value of t_MCS for each Stretch selection.
M2 M1 M0
000
001
010
011
100
101
110
111
MOVX Cycles
2 machine cycles
3 machine cycles
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t_MCS
0
4 t_CLCL
8 t_CLCL
12 t_CLCL
16 t_CLCL
20 t_CLCL
24 t_CLCL
28 t_CLCL
Parameter
Figure
Symbol
Min
Typ
Max
Unit
Serial Port Clock Cycle Time
10
t_XLXL
12 t_CLCL
ns
SM2=0,12 clocks per cycle
4 t_CLCL
ns
SM2=1,4 clocks per cycles
Output Data Setup to Clock Rising
10
t_QVXH
12 t_CLCL
ns
SM2=0,12 clocks per cycle
4 t_CLCL
ns
SM2=1,4 clocks per cycles
Output Data Hold to Clock Rising
10
t_XHQX
12 t_CLCL
ns
SM2=0,12 clocks per cycle
4 t_CLCL
ns
SM2=1,4 clocks per cycles
Input Data Hold to Clock Rising
10
t_XHDX
12 t_CLCL
ns
SM2=0,12 clocks per cycle
4 t_CLCL
ns
SM2=1,4 clocks per cycles
Clock Rising Edge to Input Data Valid
10
t_XHDV
12 t_CLCL
ns
SM2=0,12 clocks per cycle
4 t_CLCL
ns
SM2=1,4 clocks per cycles
V_IH1
t_CHCX
0.8V
t_CLCH
t_CLCX
t_CLCL
t_CHCL
Figure 4 External Clock Drive waveform
2.0V
2.0V
Test Points
0.8V
0.8V
2.0V
0.8V
Floating
2.0V
0.8V
Notes:
AC inputs during testing are driven at 2.4V for logic “HIGH” and
0.45V for logic “LOW”. Timing measurements are at 2.0V for
logic “HIGH” and 0.8V for logic “LOW”
Notes:
The float state is define as the point which PORT 0 pins sinks
3.2mA or source 400µA at the voltage test level.
Figure 5 AC Testing Input/Output
Figure 6 AC Testing, Floating Waveform
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM89T16R1 V1.0 JANUARY 2005
11