SM59264_06 Datasheet, PDF (19/36 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller with 128KB flash & 1KB RAM & TWSI & SPWM embedded

SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
SPWM Registers -SPWM Control Register (SPWMC, $A3)
bit-7
Read / Write:
Reset value:
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
SPFS1
R/W
0
SPFS[1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock.
bit-0
SPFS0
R/W
0
SPFS1
0
0
1
1
SPFS0
0
1
0
1
Divider
2
4
8
16
SPWM clock, Fosc=20MHz
10MHz
5MHz
2.5MHz
1.25MHz
SPWM clock, Fosc=24MHz
12MHz
6MHz
3MHz
1.5MHz
SPWM Registers -SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4)
Read / Write:
Reset value:
bit-7
SPWMD
[4:0]4
R/W
0
SPWMD
[4:0]3
R/W
0
SPWMD
[4:0]2
R/W
0
SPWMD
[4:0]1
R/W
0
SPWMD
[4:0]0
R/W
0
BRM
[2:0]2
R/W
0
BRM
[2:0]1
R/W
0
bit-0
BRM
[2:0]0
R/W
0
SPWMD[4:0] : content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0] : will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[2:0]
000
001
010
011
100
101
110
111
Number of SPWM cycles inserted in an 8-cycle frame
0
1
2
3
4
5
6
7
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #08H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3
; Enable P1.3 as SPWM output pin
Specifications subject to change without notice contact your sales representatives for the most recent information.
19
Ver 2.1 SM59264 08/2006