SM59264_06 Datasheet, PDF (10/36 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller with 128KB flash & 1KB RAM & TWSI & SPWM embedded

SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
Read data flash: Using direct external addressing mode (by instruction MOVX). Reading on-chip data flash will be
the same as reading external RAM with MOVX instruction.
For example, MOVX A, @DPTR or MOVX A, @Ri ; i=0,1
instruction with 16-bit addressing space.
Write data flash: Using ISP ‘byte program’ function will have to set the FAU0 bit at first.
Erase data flash: Including ISP ‘chip erase’ function and ‘page erase’ function. When using ‘chip erase’
function, it will erase all the 64K byte data flash plus 64K byte program ROM flash except
the ISP service program space if lock bit ‘N’ been configured.
Chip protect flash: Using ISP ‘chip protect’ function will protect the 64K byte data flash plus 64K byte
program ROM flash from read out. Once flash been protected, the content read will be all
‘00’.
For ‘byte program’ and ‘page erase’ flash-address-dependent ISP functions, user need to specify the FAU0 bit (=FA16)
of ISPC ($F7) at first for doing with data flash space. The 64K data flash also can be programmed or erased on writer.
1.3.1 Second Data Pointer Register - RCON ($85) and MOVX @Ri, i=1,2 with read function
Using RCON register with MOVX @Ri, i=0,1 instruction enables SM59264 has second Data Pointer Register (DPTR)
with read function only. The content of RCON register determines high byte address of 64KB data flash while content
of MOVX@Ri instruction determines low byte address. This feature similar to DPH and DPL register of MOVX @
DPTR instruction but with read function only. Using MOVX @Ri instruction to write data to the data flash will have no
effect.
System Control Register (SCONF, $BF)
bit-7
bit-0
Read / Write:
Reset value:
WDR
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
DFEN
R/W
0
ISPE
R/W
0
OME
R/W
0
ALEI
R/W
0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1, The bit 7 (WDR) of
SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should
check WDR bit whenever un-predicted reset happened.
DFEN: 64K Data Flash enable bit. The default setting of DFEN bit is 0 (disable).
ISPE: ISP enable bit
OME: 768 bytes on-chip RAM enable bit, The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte
RAM. The default setting of OME bit is 0 (disable).
ALEI: ALE output inhibit bit, to reduce EMI, Setting bit 0 (ALEI) of SCONF can inhibit the clock
signal in Fosc/6Hz output to the ALE pin.
Specifications subject to change without notice contact your sales representatives for the most recent information.
10
Ver 2.1 SM59264 08/2006