TC1550_08 Datasheet, PDF (1/5 Pages) Supertex, Inc – N- and P-Channel Enhancement-Mode Dual MOSFET

TC1550
N- and P-Channel
Enhancement-Mode Dual MOSFET
Features
► 500V breakdown voltage
► Independent N- and P-channels
► Electrically isolated N- and P-channels
► Low input capacitance
► Fast switching speeds
► Free from secondary breakdowns
► Low input and output leakage
Applications
► High voltage pulsers
► Amplifiers
► Buffers
► Piezoelectric transducer drivers
► General purpose line drivers
General Description
The Supertex TC1550 consists of a high voltage N-channel and
P-channel MOSFET in an 8-Lead SOIC package. This is an
enhancement-mode (normally-off) transistor utilizing an advanced
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this device
is free from thermal runaway and thermally induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Ordering Information
Package Option
Device
8-Lead SOIC
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
TC1550
TC1550TG-G
-G indicates package is RoHS compliant (‘Green’)
BV_DSS/BV_DGS
N-Channel
(V)
P-Channel
(V)
500
-500
R_DS(ON)
(Max)
N-Channel
(Ω)
P-Channel
(Ω)
60
125
Pin Configuration
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BV_DSS
BV_DGS
±20V
Operating and storage temperature -55°C to + 150°C
Soldering temperature^*
300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
DP
DP
DN
DN
GP
SP
GN
SN
8-Lead SOIC (TG)
(top view)
Product Marking
YYWW
C1550
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
8-Lead SOIC (TG)
* Distance of 1.6mm from case for 10 seconds.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: [phone] ● www.supertex.com