SMH4044 Datasheet, PDF (15/20 Pages) Summit Microelectronics, Inc. – Compact PCI Hot-Swap Controller With IPMI Support

SMH4044
Preliminary
BUS INTERFACE
GENERAL DESCRIPTION
The I²C bus is a two-way, two-line serial communication
between different integrated circuits. The two lines are:
a serial Data line (SDA) and a serial Clock line (SCL). All
Summit Microelectronics parts support a 100kHz clock
rate, and some support the alternative 400kHz clock.
Check Table 2 for the value of fSCL. The SDA line must
be connected to a positive supply by a pull-up resistor
located on the bus. Summit parts have Schmitt Trigger
inputs on both lines. See Figure 6 and Table 2 for
waveforms and timing on the bus. One bit of Data is
transferred during each Clock pulse. The Data must
remain stable when the Clock is high.
tR
tF
tHIGH
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
SDA In
tAA
tDH
SDA Out
Figure 6. Memory Timing
Symbol
Parameter
f_SCL
t_LOW
t_HIGH
t_BUF
t_SU:STA
t_HD:STA
t_SU:STO
t_AA
t
DH
t_R
t_F
t_SU:DAT
t_HD:DAT
TI
SCL clock frequency
Clock low period
Clock high period
Bus free time (1)
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time (1)
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time (1)
Data In hold time (1)
Noise filter SCL and SDA (1)
t_WR
Write cycle time
Note: (1) These values are guaranteed by design.
Conditions
Before new transmission
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA change
Noise suppression
Table 2. Memory Timing
SUMMIT MICROELECTRONICS, Inc.
2057 1.x 8/16/01
2057 Fig06
Min.
0
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
250
0
Max.
100
3.5
1000
300
100
5
Units
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ms
2057 Table02
15