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SPC56EC74L7 Datasheet, PDF (97/118 Pages) STMicroelectronics – 32-bit MCU family built on the Power Architecture® for automotive body electronics applications
SPC564Bxx - SPC56ECxx
Electrical Characteristics
Table 50. DSPI timing (continued)
Spec
Characteristic
Symbol
Min
Unit
Max
Slave Hold Time
—
(SS active to SCK hold time)
Slave Access Time
5 (SS active to SOUT valid)(4)
tHSS
10
tA
—
—
ns
42
ns
Slave SOUT Disable Time
6
(SS inactive to SOUT High-Z or invalid)
7 CSx to PCSS time
8 PCSS to PCSx time
Data Setup Time for Inputs
Master (MTFE = 0)
9 Slave
Master (MTFE = 1, CPHA = 0)(5)
Master (MTFE = 1, CPHA = 1)
Data Hold Time for Inputs
Master (MTFE = 0)
10 Slave
Master (MTFE = 1, CPHA = 0)(5)
Master (MTFE = 1, CPHA = 1)
Data Valid (after SCK edge)
Master (MTFE = 0)
11 Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Data Hold Time for Outputs
Master (MTFE = 0)
12 Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tDIS
—
tPCSC
0
tPASC
0
36
tSUI
5
36
36
0
tHI
4
0
0
—
tSUO
—
—
—
0(6)
tHO
9.5
0(7)
0(8)
25
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
12
ns
37
ns
12
ns
12
ns
—
ns
—
ns
—
ns
—
ns
1. This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this
table.
Δ 2. The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For SPC564B74 and
SPC56EC74, the spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > tCSC .
Δ 3. The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For SPC564B74 and
SPC56EC74, the spec value of tASC will be attained only if TDSPI x PASC x ASC > tASC.
4. The parameter value is obtained from tSUSS and tSUO for slave.
5. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00.
6. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is −2 ns.
7. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is −2 n.
8. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is −2 ns.
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