SPC56EC74L7 Datasheet, PDF (53/118 Pages) STMicroelectronics – 32-bit MCU family built on the Power Architecture® for automotive body electronics applications

SPC564Bxx - SPC56ECxx
Electrical Characteristics
Table 11. Recommended operating conditions (5.0 V) (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
I_INJPAD
SR
Injected input current on any
during overload condition
pin
—
–5
5
mA
I_INJSUM
SR
Absolute sum of all injected input
currents during overload condition
—
–50
50
TV_DD
SR
V_{DD_HV_A} slope to ensure correct
power up⁽⁸⁾
—
—
—
0.5
0.5
V/µs
—
V/min
T_{A C-Grade Part} SR Ambient temperature under bias
—
T_{J C-Grade Part} SR Junction temperature under bias
—
T_{A V-Grade Part} SR Ambient temperature under bias
—
T_{J V-Grade Part} SR Junction temperature under bias
—
T_{A M-Grade Part} SR Ambient temperature under bias
—
T_{J M-Grade Part} SR Junction temperature under bias
—
−40
85
−40
110
−40
105
−40
130
−40
125
°C
−40
150
1. 100 nF EMI capacitance and 10 µF bulk capacitance needs to be provided between each V_{DD_HV_A/HV_B}/V_{SS_HV} pair.
2. Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC electrical characteristics (startup time, IDD, negative
resistance, ESR and duty cycle) will not be guaranteed to stay within the stated limits when operating below 4.5 V and
above 3.6 V. However, OSC functionality is guaranteed within the entire range (3.0 V–5.5 V).
3. 100 nF EMI capacitance and 40 µF bulk capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV} supply pair.
4. This voltage is internally generated by the device and no external voltage should be supplied.
5. 100 nF capacitance needs to be provided between V_{DD_HV_(ADC0/ADC1)}/V_{SS_HV_(ADC0/ADC1)} pair.
6. Both the relative and the fixed conditions must be met. For instance: If V_{DD_HV_A} is 5.9 V, V_{DD_HV_ADC0} maximum value is
6.0 V then, despite the relative condition, the max value is V_{DD_HV_A} + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from V_{DD_HV_B} domain hence VDD_HV_ADC1 should be
within ±100 mV of V_{DD_HV_B} when these channels are used for ADC_1.
8. Guaranteed by device validation.
Note:
SRAM retention guaranteed to LVD levels.
4.5
Thermal characteristics
4.5.1 Package thermal characteristics
Table 12. LQFP thermal characteristics⁽¹⁾
Symbol
C
Parameter
Conditions⁽²⁾
Pin
count
R_θJA
CC
D
Thermal resistance,
junction-to-ambient
natural convection
Single-layer
board—1s
176
208
R_θJA
CC
D
Thermal resistance,
junction-to-ambient
natural convection
Four-layer
board—2s2p⁽⁵⁾
176
208
Value⁽³⁾
Unit
Min
Typ
Max
—
—
44.4⁽⁴⁾ °C/W
—
—
TBD °C/W
—
—
36.1 °C/W
—
—
TBD °C/W
Doc ID 17478 Rev 4
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