STM32F103VET6 Datasheet, PDF (95/130 Pages) STMicroelectronics – High-density performance line

STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
I²S - SPI characteristics
Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I²S
are derived from tests performed under ambient temperature, f_PCLKx frequency and V_DD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I²S).
Table 53. SPI characteristics
Symbol
Parameter
Conditions
Min Max Unit
f_SCK
1/t_c(SCK)
SPI clock frequency
Master mode
Slave mode
18
MHz
18
t_r(SCK)
t_f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
30
70
%
t_su(NSS)(1) NSS setup time
Slave mode
4t_PCLK
t_h(NSS)(1) NSS hold time
Slave mode
2t_PCLK
t_w(SCKH)(1)
t_w(SCKL)(1)
SCK high and low time
Master mode, f_PCLK = 36 MHz,
presc = 4
50
60
t_su(MI) ⁽¹⁾
t_su(SI)(1)
Data input setup time
Master mode
Slave mode
5
5
t_h(MI) ⁽¹⁾
Master mode
5
Data input hold time
t_h(SI)(1)
Slave mode
4
t_a(SO)(1)(2) Data output access time Slave mode, f_PCLK = 20 MHz
0
t_{dis(SO)(1)(3)} Data output disable time Slave mode
2
t_v(SO) ⁽¹⁾ Data output valid time Slave mode (after enable edge)
t_v(MO)(1) Data output valid time Master mode (after enable edge)
t_h(SO)(1)
t_h(MO)(1)
Data output hold time
Slave mode (after enable edge) 15
Master mode (after enable edge) 2
ns
3t_PCLK
10
25
5
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Doc ID 14611 Rev 8
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