TDA7340G Datasheet, PDF (9/27 Pages) STMicroelectronics – AUDIO SIGNAL PROCESSOR

TDA7340G
NOTES TO THE CHARACTERISTICS (continued)
3) SCA (SUBSIDIARY COMMUNICATIONS AUTHORIZATION)
α67
=
V_O(signal) (at1KHz)
V_O (spurious) (at9KHZ)
;
f_s
=
(2
x
38KHz)
-
67KHz
measured with : 81% mono signal; 9% pilot signal; fm=1KHz;
10% SCA - subcarrier (fs = 67KHz, unmodulated)
4) ACI (ADJACENT CHANNEL INTERFERENCE)
α114
=
VO (signal) (at1KHz)
VO (spurious) (at4KHZ)
;
f_s
=
110KHz -
(3
x
38KHz)
α190
=
V_O (signal) (at1KHz)
VO (spurious) (at4KHZ)
;
fs
=
186KHz -
(5
x
38KHz)
measured with : 90% mono signal; 9% pilot signal; fm=1KHz; 1% spurious signal
(fs = 110KHz or 186KHz, unmodulated)
5) Control range typ 11% of VR (see figure 2)
6) Control range typ 30% of VR (see figure 1)
7) All thresholds are measured by using a pulse with TR = 2µs, THIGH = 2µs and TF = 10µs.
The repetition rate must not increase the PEAK voltage.
8) NBT represent the STDEC bit pair D₆, D₅ for the noise blanker trigger threshold
NAT represent the SPKR_LF bit pair D₇, D₅ for the noise controlled trigger threshold
9) OVD represent the SPKR_LR bit pair D7, D6 for the over deviation detector
10) FSC represent the SPKR_RF bit pair D7, D6 for the field strength control
11) The TDA7340G has a dedicated internal circuitry providing a soft power-on. The I2C bus data
programmation must start after the reference DC level has reached the target Vs/2 value,
otherwise a pop can be generated. The Cref pin and Out pins rise time at power on are riported
in Figg.4, 5, 6 for Cref values of 4.7uF, 10uF, 22uF.
12) The CDL- and CDR- can be shortcircuited in applications providing 3 wires CD signal.
L+
L- ^∼=R-
CD
R+
L+
L-
TDA7340G
R-
R+
D95AU352
13)The AGND and DGND layout wires must be kept separated. A 50Ω resistor is recommend to be put
as far as possible from the device.
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