STD95NH02L Datasheet, PDF (9/11 Pages) STMicroelectronics – N-CHANNEL 24V - 0.0039ohm - 80A DPAK ULTRA LOW GATE CHARGE STripFET MOSFET

STD95NH02L
Appendix A: Buck Converter Power Losses Estimation
DESCRIPTION
The power losses associated with the FETs in a
Synchronous Buck converter can be estimated us-
ing the equations shown in the table below. The for-
mulas give a good approximation, for the sake of
performance comparison, of how different pairs of
devices affect the converter efficiency. However a
very important parameter, the working temperature,
is not considered. The real device behavior is really
dependent on how the heat generated inside the de-
vices is removed to allow for a safer working junc-
tion temperature.
The low side (SW2) device requires:
- Very low RDS(on) to reduce conduction losses
- Small Q_gls to reduce the gate charge losses
- Small C_oss to reduce losses due to output
capaci tance
- Small Q_rr to reduce losses on SW1 during its
turn-on
- The C_gd/C_gs ratio lower than V_th/V_GG ratio
especially with low drain to source voltage
to avoid the cross conduction phenomenon
The high side (SW1) device requires:
- Small R_g and L_s to allow higher gate current
peak and to limit the voltage feedback on the gate
- Small Q_g to have a faster commutation and
to reduce gate charge losses
- Low R_DS(on) to reduce the conduction losses
Pconduction
Pswitching
High Side Switch (SW1)
R * _DS(on)SW1 I^2L *δ
Low Side Switch (SW2)
R * _DS(on)SW2 I^2L *(1−δ)
V_in
*(Q_gsth(SW1)+
Q_gd(SW1))
*f
*
I_L
I_g
Zero Voltage Switching
P_diode ^Recovery
Conduction
Pgate(Q )
G
PQoss
Not Applicable
Not Applicable
Q_g(SW1)*V_gg *f
V_in *Q_oss(SW1)*f
2
1_{Vin *Qrr(SW2)*f}
V_f(SW2)*I_L *t *f _deadtime
Q_gls * _(SW2) V_gg *f
V_in *Q_oss(SW2)*f
2
Parameter
δ
Q_gsth
Q_gls
Pconduction
Pswitching
Pdiode
Pdiode
P_Qoss
Meaning
Duty-Cycle
Post Threshold Gate Charge
Third Quadrant Gate Charge
On State Losses
On-off Transition Losses
Conduction and Reverse Recovery Diode Losses
Gate Drive Losses
Output Capacitance Losses
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