M24C02-WMN6P Datasheet, PDF (9/38 Pages) STMicroelectronics – Enhanced ESD/latch-up protection, More than 40-year data retention

M24C16, M24C08, M24C04, M24C02, M24C01
Signal description
2.4
2.4.1
2.4.2
2.4.3
2.4.4
Supply voltage (V_CC)
Operating supply voltage V_CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V_CC voltage
within the specified [V_CC(min), V_CC(max)] range must be applied (see Table 6, Table 7 and
Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the
V_CC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
V_CC/V_SS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t_W).
Power-up conditions
The V_CC voltage has to rise continuously from 0 V up to the minimum V_CC operating voltage
defined in Table 6, Table 7 and Table 8 and the rise time must not vary faster than 1 V/µs.
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up (continuous rise of V_CC), the device does not respond to any
instruction until V_CC reaches the power-on-reset threshold voltage (this threshold is lower
than the minimum V_CC operating voltage defined in Table 6, Table 7 and Table 8). When
V_CC passes over the POR threshold, the device is reset and enters the Standby Power
mode. The device, however, must not be accessed until V_CC reaches a valid and stable V_CC
voltage within the specified [V_CC(min), V_CC(max)] range.
In a similar way, during power-down (continuous decrease in V_CC), as soon as V_CC drops
below the power-on-reset threshold voltage, the device stops responding to any instruction
sent to it.
Power-down conditions
During power-down (continuous decrease in V_CC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Figure 5. Maximum R_P value versus bus parasitic capacitance (C) for an I²C bus
100
10
4 kΩ
R_bus
Here R_bus × C_bus = 120 ns
× _Cbus
= _{400 ns}
1
10
30 pF
100
Bus line capacitor (pF)
When t_LOW = 1.3 µs (min value for
f_C = 400 kHz), the R_bus × C_bus
time constant must be below the
400 ns time constant line
represented on the left.
V_CC
R_bus
1000
I²C bus
master
SCL
SDA
M24xxx
C_bus
ai14796b
Doc ID 5067 Rev 17
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