M24C02-WMN6P Datasheet, PDF (6/38 Pages) STMicroelectronics – Enhanced ESD/latch-up protection, More than 40-year data retention

Description
1
Description
M24C16, M24C08, M24C04, M24C02, M24C01
These I²C-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02 and
M24C01).
Figure 1. Logic diagram
VCC
3
E0-E2
SCL
WC
M24Cxx
SDA
VSS
AI02033
I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C
bus definition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9^th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Table 2. Signal names
Signal name
Function
E0, E1, E2
SDA
SCL
WC
V_CC
V_SS
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Direction
Input
Input/output
Input
Input
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Doc ID 5067 Rev 17