ST72F262G2B5 Datasheet, PDF (89/172 Pages) STMicroelectronics – 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

ST72260Gx, ST72262Gx, ST72264Gx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4 Functional Description
11.5.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 53. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 53).
– Two control registers (SCICR1 & SCICR2)
The TDO pin is in low state during the start bit.
– A status register (SCISR)
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
PR)
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section
11.5.7for the definitions of each bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 54. Word Length Programming
9-bit Word length (M bit is set)
Data Frame
Possible
Parity
Bit
Next Data Frame
Next
Start
Bit ^Bit0
Bit1
Bit2
Bit3
Bit4 Bit5
Bit6
Bit7 Bit8
Stop
Bit
Start
Bit
Start
Idle Frame
Bit
Break Frame
Extra ^Start
’1’ ^Bit
8-bit Word length (M bit is reset)
Data Frame
Start
Bit ^{Bit0 Bit1 Bit2 Bit3 Bit4 Bit5}
Possible
Parity
Bit
Bit6
Bit7
Stop
Bit
Next Data Frame
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame
Extra
’1’
Start
Bit
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