ST72F262G2B5 Datasheet, PDF (103/172 Pages) STMicroelectronics – 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

ST72260Gx, ST72262Gx, ST72264Gx
11.6 I²C BUS INTERFACE (I2C)
11.6.1 Introduction
The I²C Bus Interface serves as an interface be-
tween the microcontroller and the serial I²C bus. It
provides both multimaster and slave functions,
and controls all I²C bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast I²C
mode (400kHz).
11.6.2 Main Features
■ Parallel-bus/I²C protocol converter
■ Multi-master capability
■ 7-bit/10-bit Addressing
■ SMBus V1.1 Compliant
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
I²C Master Features:
■ Clock generation
■ I²C bus busy flag
■ Arbitration Lost Flag
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
I²C Slave Features:
■ Stop bit detection
■ I²C bus busy flag
■ Detection of misplaced start or stop condition
■ Programmable I²C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
11.6.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
Figure 57. I²C BUS Protocol
SDA
MSB
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I²C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I²C bus
and a Fast I²C bus. This selection is made by soft-
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 57.
ACK
SCL
1
2
8
9
START
CONDITION
STOP
CONDITION
VR02119B
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