ST72F262G2B5 Datasheet, PDF (104/172 Pages) STMicroelectronics – 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES

ST72260Gx, ST72262Gx, ST72264Gx
I²C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The I²C interface address and/or general call ad-
dress can be selected by software.
The speed of the I²C interface may be selected
between Standard (up to 100KHz) and Fast I²C
(up to 400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 58. I²C Interface Block Diagram
The SCL frequency (F_scl) is controlled by a pro-
grammable clock divider which depends on the
I²C bus mode.
When the I²C cell is enabled, the SDA and SCL
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I²C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
104/172