STM32F103ZCH6 Datasheet, PDF (86/130 Pages) STMicroelectronics – High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 46. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO input low
level voltage
V_{IL IO FT(1) input low level}
voltage
–0.3
0.28*(V_DD-2 V)+0.8 V V
–0.3
0.32*(V_DD-2 V)+0.75 V V
Standard IO input high
level voltage
V_{IH IO FT(1) input high level VDD > 2 V}
voltage
V_DD ≤ 2 V
Standard IO Schmitt
trigger voltage
V_hys ^{hysteresis(2)}
IO FT Schmitt trigger
voltage hysteresis⁽²⁾
0.41*(V_DD-2 V)+1.3 V
0.42*(V_DD-2 V)+1 V
200
5% V_DD(3)
V_DD+0.3
V
5.5
V
5.2
mV
mV
V_SS ≤ V_IN ≤ V_DD
I_lkg Input leakage current ^{(4) Standard I/Os}
V_IN= 5 V, I/O FT
±1
µA
3
R_PU
Weak pull-up equivalent
resistor⁽⁵⁾
V_IN = V_SS
30
40
50
kΩ
R_PD
Weak pull-down
equivalent resistor⁽⁵⁾
V_IN = V_DD
30
40
50
kΩ
C_IO I/O pin capacitance
5
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than V_DD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 42 and Figure 43 for standard I/Os, and
in Figure 44 and Figure 45 for 5 V tolerant I/Os.
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