ST10F272Z2_08 Datasheet, PDF (85/189 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

ST10F272Z2
System reset
Figure 18. Asynchronous power-on RESET (EA = 0)
≥ 1.2 ms (for resonator oscillation + PLL stabilization)
≥ 10.2 ms (for crystal oscillation + PLL stabilization)
≥ 1 ms (for on-chip VREG stabilization)
V_DD
V₁₈
XTAL1
RPD
RSTIN
RSTF
(After Filter)
P0[15:13]
P0[12:2]
P0[1:0]
ALE
3..8 TCL¹⁾
...
≥ 50 ns
≤ 500 ns
3..4 TCL
transparent
transparent
not transparent
not t.
not t.
not t.
8 TCL
RST
Latching point of Port0 for
system start-up configuration
Note 1. 3 to 8 TCL depending on clock source selection.
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Reset circuitry chapter and Figures 30, 31 and 32.
It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
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