ST10F272Z2_08 Datasheet, PDF (161/189 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

ST10F272Z2
Figure 49. ST10F272Z2 PLL jitter
±5
16MHz 24MHz 32MHz 40MHz
±4
Electrical characteristics
64MHz
±3
±2
±1
T_JIT
0
0
200
400
600
800 1000 1200 1400
N (CPU clock periods)
25.8.10
Note:
PLL lock / unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from
the PLL input: in this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency F_free). This feature allows to recover from a
crystal failure occurrence without risking to go in an undefined configuration: the system is
provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between reference clock and PLL input can be restored only by a hardware reset,
or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration
of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized
high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not
sufficient to get the PLL locked starting from free-running mode).
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