ST10F272Z2_08 Datasheet, PDF (146/189 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

Electrical characteristics
ST10F272Z2
25.7 A/D converter characteristics
V_DD = 5 V ± 10%, V_SS = 0 V, T_A = –40 to +125 °C, 4.5 V ≤ V_AREF ≤ V_DD,
V_SS ≤ V_AGND ≤ V_SS + 0.2 V
Table 68. A/D converter characteristics
Parameter
Symbol
Analog Reference voltage 1)
Analog Ground voltage
Analog Input voltage 2)
Reference supply current
Sample time
Conversion time
Differential Non Linearity ⁶⁾
Integral Non Linearity ⁶⁾
Offset Error ⁶⁾
Total unadjusted error ⁶⁾
V_AREF SR
V_AGND SR
V_AIN SR
I_AREF CC
t_S CC
t_C CC
DNL CC
INL CC
OFS CC
TUE CC
Coupling Factor between inputs 3) 7)
Input Pin Capacitance ^{3) 8)}
K CC
C_P1 CC
C_P2 CC
Sampling Capacitance ^{3) 8)}
C_S CC
Analog Switch Resistance ^{3) 8)}
R_SW CC
R_AD CC
Limit Values
min.
4.5
V_SS
V_AGND
–
–
1
3
–1
–1.5
–1.5
–2.0
–5.0
–7.0
–
–
–
–
–
–
–
max.
V_DD
V_SS + 0.2
V_AREF
5
1
–
–
+1
+1.5
+1.5
+2.0
+5.0
+7.0
10^–6
3
4
6
3.5
600
1600
1300
Unit
Test Condition
V
V
V
mA
Running mode ³⁾
µA
Power Down mode
µs
4)
µs
5)
LSB No overload
LSB No overload
LSB No overload
Port5
LSB Port1 - No overload ³⁾
Port1 - Overload ³⁾
–
On both Port5 and Port1
pF
Port5
pF
Port1
pF
Port5
W
Port1
W
1. V_AREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200µA) on
main V_DD is added due to internal analogue circuitry not completely turned off: so, it is suggested to
maintain the V_AREF at V_DD level even when not in use, and eventually switch off the A/D Converter circuitry
setting bit ADOFF in ADCON register.
2. V_AIN may exceed V_AGND or V_AREF up to the absolute maximum ratings. However, the conversion result in
these cases will be 0x000_H or 0x3FF_H, respectively.
3. Not 100% tested, guaranteed by design characterization.
4. During the sample time the input capacitance C_AIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within t_S.
After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion
result.
Values for the sample clock t_S depends on programming and can be taken from Table 69: A/D converter
programming.
5. This parameter includes the sample time t_S, the time for determining the digital result and the time to load
the result register with the conversion result. Values for the conversion clock t_CC depend on programming
and can be taken from next Table 69.
6. DNL, INL, OFS and TUE are tested at V_AREF = 5.0 V, V_AGND = 0V, V_DD = 5.0 V. It is guaranteed by design
characterization for all other voltages within the defined voltage range.
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