ST7L34 Datasheet, PDF (80/234 Pages) –

On-chip peripherals
ST7L34 ST7L35 ST7L38 ST7L39
The four PWM signals can have the same frequency (f_PWM) or can have two different
frequencies. This is selected by the ENCNTR2 bit which enables single timer or dual timer
mode (see Figure 35: Single timer mode (ENCNTR2 = 0) on page 79 and Figure 36: Dual
timer mode (ENCNTR2 = 1) on page 79).
The frequency is controlled by the counter period and the ATR register value. In dual timer
mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2
and ATR2.
f_PWM = f_COUNTER/(4096 - ATR)
Following the above formula, if f_COUNTER is 4 MHz_, the maximum value of f_PWM is 2 MHz
(ATR register value = 4094), the minimum value is 1 kHz (ATR register value = 0).
Obsolete ^{Product(s) - Obsolete Product(s) Note:}
Duty cycle
The duty cycle is selected by programming the DCRx registers. These are preload registers.
The DCRx values are transferred in active duty cycle registers after an overflow event if the
corresponding transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls
the PWMx outputs driven by counter 2.
PWM generation and output compare are done by comparing these active DCRx values
with the counter.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1/(4096 - ATR)
Where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be
obtained by changing the polarity.
At reset, the counter starts counting from 0.
When an upcounter overflow occurs (OVF event), the preloaded duty cycle values are
transferred to the active duty cycle registers and the PWMx signals are set to a high level.
When the upcounter matches the active DCRx value, the PWMx signals are set to a low
level. To obtain a signal on a PWMx pin, the contents of the corresponding active DCRx
register must be greater than the contents of the ATR register.
For ROM devices only: The PWM can be enabled/disabled only in overflow ISR, otherwise
the first pulse of PWM can be different from expected one because no force overflow
function is present.
The maximum value of ATR is 4094 because it must be lower than the DCR value, which in
this case must be 4095.
Polarity inversion
The polarity bits can be used to invert any of the four output signals. The inversion is
synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2
register is set (reset value). See Figure 37.
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