ST7L34 Datasheet, PDF (155/234 Pages) –

ST7L34 ST7L35 ST7L38 ST7L39
On-chip peripherals
Table 71. SCICR1 register description⁽¹⁾ (continued)
Bit Name
Function
Word length
This bit determines the word length. It is set or cleared by software.
4M
0: 1 start bit, 8 data bits, 1 stop bit
1: 1 start bit, 9 data bits, 1 stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
Wake-up method
This bit determines the SCI wake-up method. It is set or cleared by software.
3 WAKE 0: Idle line
1: Address mark
) Note: If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.
t(s ^{Parity control enable}
Produc ^{2 PCE}
This bit is set and cleared by software. It selects the hardware parity control for LIN
identifier parity check.
0: Parity control disabled
1: Parity control enabled
When a parity error occurs, the PE bit in the SCISR register is set.
te 1 - Reserved, must be kept cleared
le _{Parity interrupt enable}
- ^{Obso 0 PIE}
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). The parity error involved can be a byte parity error (if bit
PCE is set and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is
set).
) 0: Parity error interrupt disabled
t(s ^{1: Parity error interrupt enabled}
c 1. Bits 7:3 and bit 0 have the same function as in SCI mode; please refer to Control register 1 (SCICR1) on
u ^{page 136.}
rod _{Control register 2 (SCICR2)}
te ^P _SCICR2
Reset value: 0000 0000 (00h)
le ₇
6
5
4
3
2
1
0
so _TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Ob _R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Doc ID 11928 Rev 8
155/234