XRAG2_08 Datasheet, PDF (8/33 Pages) STMicroelectronics – 432-bit UHF, EPCglobal Class1 Generation2 and ISO 18000-6C, contactless memory chip with user memory

XRAG2 memory mapping
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XRAG2 memory mapping
XRAG2
The XRAG2 is a 432-bit memory organized in three memory banks (without the user
memory) or four memory bank (with the user memory) depending on the size of the EPC
code chosen by the user. Each bank is organized as 16-bit words. The reader can read part
or all of each memory bank by 16-bit words. Using the Write command, the device is written
a 16-bit word at a time. The BlockWrite command allows readers to write up to 4 words at a
time. The BlockErase command allows readers to erase several words at a time (from two
words to the entire memory bank).
The bank number and memory organization depend on the size of the EPC contents
programmed in the EPC_length field stored in the first five bits of the Protocol Control (PC)
word.
The sixteen Protocol Control bits are located at memory bit addresses 10h-1Fh of the EPC
bank, as defined in the EPCglobal Class 1 generation 2 RFID UHF specification, revision
1.0.9.
The XRAG2 memory organization is automatically adjusted under the following conditions:
● for EPC_length values below or equal to 9_d, the XRAG2 memory organization features
a:
– 64-bit Reserved bank,
– 176-bit EPC bank for 128-bit EPC code storage,
– 64-bit TID bank,
– 128-bit User bank,
The memory map corresponding to this configuration is shown in Figure 4.
● for EPC_length values above 9_d, the XRAG2 memory organization features a:
– 64-bit Reserved bank,
– 304-bit EPC bank for 256-bit EPC code storage,
– 64-bit TID bank.
The memory map corresponding to this configuration is shown in Figure 5.
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