XRAG2_08 Datasheet, PDF (6/33 Pages) STMicroelectronics – 432-bit UHF, EPCglobal Class1 Generation2 and ISO 18000-6C, contactless memory chip with user memory

Description
1
Description
XRAG2
The XRAG2 is a full-featured, low-cost integrated circuit for use in radio frequency
identification (RFID) transponders (XRAG2s) operating at UHF frequencies. It is a 432-bit
memory organized as 3 or 4 memory banks of 16-bit words as shown in Figure 4 and
Figure 5.
When connected to an antenna, the operating power is derived from the RF energy
produced by the RFID reader and incoming data are demodulated and decoded from the
received double-side band amplitude shift keying (DSB-ASK), single-side band amplitude
shift keying (SSB-ASK) or phase-reversal amplitude shift keying (PR-ASK) modulation
signal. Outgoing data are generated by antenna reflectivity variation using either FM0 or the
Miller bit coding principle (chosen by the reader).
Communications between the reader and the XRAG2 are Half-duplex, which means that the
XRAG2s does not decode reader commands while back scattering.
The data transfer rate is defined by the local UHF frequency regulation.
The XRAG2 complies with the EPC Global Class-1 Generation-2 UHF RFID specification,
revision 1.0.9, for the radio-frequency power and signal interface.
Figure 1. Pad connections
Power
Supply
Regulator
AC1
432 bit
ASK
EEPROM Demodulator
memory
AC0
Reflecting
Modulator
Figure 2. Die floor plan
AI12306
(GND) AC0
AC1
ai12307
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