M14256 Datasheet, PDF (8/12 Pages) STMicroelectronics – Memory Card IC 256/128 Kbit Serial I²C Bus EEPROM

M14256, M14128
Figure 8. Read Mode Sequences
CURRENT
ADDRESS
READ
ACK
NO ACK
DEV SEL
DATA OUT
R/W
RANDOM
ADDRESS
READ
ACK
ACK
ACK
ACK
NO ACK
DEV SEL *
BYTE ADDR BYTE ADDR
DEV SEL *
DATA OUT
R/W
R/W
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
ACK
DEV SEL
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
ACK
ACK
ACK
ACK
ACK
DEV SEL *
BYTE ADDR BYTE ADDR
DEV SEL *
DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
Note: 1. The seven most significant bits of the Device Select bytes of a Random Read (in the 1^st and 4^th bytes) must be identical.
the RW bit set to ‘1’. The memory acknowledges
this, and outputs the byte addressed. The master
must not acknowledge the byte output, and termi-
nates the transfer with a STOP condition.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. How-
ever, in this case the master does acknowledge
the data byte output, and the memory continues to
output the next byte in sequence. To terminate the
stream of bytes, the master must not acknowledge
the last byte output, and must generate a STOP
condition. The output data comes from consecu-
tive addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
counter will ‘roll-over’ and the memory will contin-
ue to output data from the start of the memory
block.
Acknowledge in Read Mode
In all read modes the memory waits for an ac-
knowledgment during the 9^th bit time. If the master
does not pull the SDA line low during this time, the
memory terminates the data transfer and switches
to its standby state.
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