M14256 Datasheet, PDF (7/12 Pages) STMicroelectronics – Memory Card IC 256/128 Kbit Serial I²C Bus EEPROM

Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by M14xxx
NO ACK
Returned
YES
Next
NO
Operation is
Addressing the
Memory
ReSTART
YES
Send
Byte Address
STOP
M14256, M14128
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI02165
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t_w) is indicated in Table 7, but the
typical time is shorter. To make use of this, an ACK
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is as follows:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a device select byte (first byte of the
new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an ACK, indicating that the memory is
ready to receive the second part of the next in-
struction (the first byte of this instruction having
been sent during Step 1).
Read Operations
Read operations are independent of the state of
the WC pin. On delivery, the memory content is set
at all “1’s” (FFh).
Current Address Read
The memory has an internal address counter.
Each time a byte is read, this counter is increment-
ed. For the Current Address Read mode, following
a START condition, the master sends a device se-
lect with the RW bit set to ‘1’. The memory ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The master must not acknowl-
edge the byte output, and terminates the transfer
with a STOP condition, as shown in Figure 8.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
This is followed by another START condition from
the master and the device select is repeated with
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