SPEAR-07-NC03 Datasheet, PDF (77/194 Pages) STMicroelectronics – Ethernet Communication Controller with USB-Host

SPEAR-07-NC03
6 Blocks description
Bit
Field
name
01
CLF
00
HCR
Reset
0b
0b
Read/Write
HCD HC
RW RW
RW RW
Description
ControlListFilled
This bit is used to indicate whether there are any
TDs on the Control list. It is set by HCD whenever it
adds a TD to an ED in the Control list.
When HC begins to process the head of the
Control list, it checks CLF. As long as
ControlListFilled is 0, HC will not start processing
the Control list. If CF is 1, HC will start processing
the Control list and will set ControlListFilled to 0.
If HC finds a TD on the list, then HC will set
ControlListFilled to 1 causing the Control list
processing to continue. If no TD is found on the
Control list, and if the HCD does not set
ControlListFilled, then ControlListFilled will still
be 0 when HC completes processing the Control
list and Control list processing will stop.
HostControllerReset
This bit is set by HCD to initiate a software reset of
HC.
Regardless of the functional state of HC, it moves
to the USBSUSPEND state in which most of the
operational registers are reset except those stated
otherwise; e.g., the InterruptRouting field of
HcControl, and no Host bus accesses are allowed.
This bit is cleared by HC upon the completion of
the reset operation. The reset operation must be
completed within 10 s. This bit, when set, should
not cause a reset to the Root Hub and no
subsequent reset signaling should be asserted to
its downstream ports.
The HcCommandStatus register is used by the Host Controller to receive commands issued by
the Host Controller Driver, as well as reflecting the current status of the Host Controller. To the
Host Controller Driver, it appears to be a "write to set" register. The Host Controller must ensure
that bits written as '1' become set in the register while bits written as '0' remain unchanged in
the register. The Host Controller Driver may issue multiple distinct commands to the Host
Controller without concern for corrupting previously issued commands. The Host Controller
Driver has normal read access to all bits.
The SchedulingOverrunCount field indicates the number of frames with which the Host
Controller has detected the scheduling overrun error. This occurs when the Periodic list does
not complete before EOF. When a scheduling overrun error is detected, the Host Controller
increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus register.
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