SPEAR-07-NC03 Datasheet, PDF (180/194 Pages) STMicroelectronics – Ethernet Communication Controller with USB-Host

6 Blocks description
SPEAR-07-NC03
Phase/Frequency Comparator: This comparator drives trough a low pass filter the VCO
control imput.
VCO: In SPEAr Net the VCO runs at 48 MHz.
Feedback Divider: In SPEAr Net this divider is set to 48.
Post Divider: In SPEAr Net this divider is set to 1.
According to the setting on the three dividers the System Frequency, connecting a 25 MHz
crystal will be:
F_OUT = 2 * Feedback Divider *F_IN / (Pre Divider) * 2^{Post Divider})
Then the system clock will be:
F_OUT = 2 * 48 * 25 / (25 * 21) = 48 MHz
This means that the CPU, the system bus and also the external DRAM will run at this
frequency.
6.17.2 Global Configuration Block
The global configuration block includes the system configuration registers, the system control/
status registers and the shared memory control/status registers.
The system configuration registers sample the value presented at the ADD lines during the
power- on reset phase. This reset phase is caused by the POWERGOOD signal driven low.
During this phase the ADD lines are configured as input; there should be resistances on the
board to drive the ADD lines with a weak high or low signal that will be latched on the registers
and will configure the system hardware and possibly the software. The PLL_BYPASS and the
JTAG_ENABLE_N conditions are propagated to the system even before the POWERGOOD
signal is asserted, to guarantee a proper setup in every case and to allow usage of JTAG before
any clock cycle is completed.
When JTAG_ENABLE_N is driven low the pins in the first column of Table 1, "Pin mapping for
JTAG interface", on page 2 change their function as defined in the second column.
6.17.3 Register Map
Address
0x3000_1C00
0x3000_1C04
0x3000_1C08
0x3000_1C0C
0x3000_1C10
0x3000_1C14
Register Name
FW_CFG
HW_CFG
GLOBAL_CONTROL
GLOBAL_STATUS
SHRAM_TEST_CTRL
SHRAM_TEST_STATUS
Access
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