SPEAR-07-NC03 Datasheet, PDF (59/194 Pages) STMicroelectronics – Ethernet Communication Controller with USB-Host

SPEAR-07-NC03
6 Blocks description
6.2.4.27 Flow Control register
Mnemonic: FCR
Address: 0x3000_341C
Default value: 0x0000_0000
Bit
Field name
31 - 16
15 - 03
02
01
00
PTIME
Reserved
PCF
FCE
FCB
Access
RW
RO
RW
RW
RW
Note:
This register is used to control the generation and reception of the Control (PAUSE Command)
frames by the MAC's Flow control block. A write to register with busy bit set to '1' triggers the
Flow Control block to generate a Control frame. The fields of the control frame are selected as
specified in the 802.3x specification and PauseTime value from this register is used in the
"Pause Time" field of the control frame. The Busy bit is set until the control frame is transferred
onto the cable. The Host has to make sure that the Busy bit is cleared before writing the
register. The Pass Control Frames bit indicates the MAC whether to pass the control frame to
the Host or not and Flow Control Enable bit enables the receive portion of the Flow Control
block.
PTIME: Pause Time. This field tells the value that is to be used in the PAUSE TIME field in the
control frame.
PCF: Pass Control Frames. When set, the control frames are passed to the Host. The MAC110
core will decode the control frame (PAUSE), disables the transmitter for the specified amount of
time. The Control Frame bit in the Receive Status (bit 25) is set and Transmitter Pause Mode
signal indicates the current state of the MAC Transmitter.
When reset, the MAC110 core will decode the control frames but will not pass the frames to the
Host. The Control Frame bit in the Receive Status (bit 25) will be set and the Transmitter Pause
Mode signal gives the current status of the Transmitter, but the Packet Filter bit in the Receive
Status is reset indication the application to flush the frame.
FCE: Flow Control Enable. When set, the MAC is enabled for operation and it will decode all the
incoming frames for control frames. When the MAC receives a valid control frame (PAUSE
command), it will disable the transmitter for the specified time.
When reset, the operation in the MAC is disabled and the MAC does not decode the frames for
control frames.
Flow Control is applicable when the MAC110 is set in Full Duplex Mode. In Half Duplex mode,
this bit will enable using Backpressure to control flow of transmitted frames to the MAC110.
FCB: Flow Control Busy. This bit should read a logic 0 before writing to the Flow Control
register. To initiate a PAUSE control frame the host must set this bit to '1'. During a transfer of
Control Frame, this bit will continue to be set to signify that a frame transmission is in progress.
After the completion of the transmission of the PAUSE control frame, the MAC will reset to '0'.
The Flow Control register should not be written to until this bit is cleared.
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